ANALOG/RF PERFORMANCE AND LINEARITY INVESTIGATION OF SI-BASED DOUBLE GATE TUNNEL FET
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Abstract
In this paper, we present a simulation study to report the effect of gate-length downscaling on the analog/RF performance and Linearity investigation of Si-based DG Tunnel FET (TFET). The different RF/analog figure-of-merits such as gm, RO, intrinsic gain, fT, fmax and GBW and 1-dB Compression point considered as important linearity matrices of a TFET are extracted and the influence of gate-length downscaling on these parameters is analyzed. Results reveals that superior RF and Linearity performance was obtained with gate-length downscaling. However, these advantages diminishes in terms of poor analog performance with gate-length downscaling. This clearly indicates a trade-off between the analog and RF performance of a down-scaled Si-based TFET. This paper concludes that Si-based TFETs have enormous potential to be a promising contender to the conventional bulk MOSFETs for realization of future generation low-power analog/RF applications.