DESIGN OF 4 BIT ROTATE LEFT NETWORK AT LOW POWER AND SMALL DELAY USING MOS TRANSISTOR AT 45 NM CHANNEL LENGTH
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Abstract
In this work the design of 4 bit rotate left network with Metal Oxide Semiconductor (MOS) transistor having channel of 45nm has been presented. To report average power consumption and delay of the network the magnitude of the voltage of control signals and signal sources has been diverse from 0.5 V to 1.2 V .The measured value of average power consumption is 19渭W and gate delay is 17.3ps at on voltage of 1 volt. The overall circuit has been simulated using Tanner SPICE (T-SPICE) software.